PDK Extraction QA Engineer

Job Details

Job Description:

Deliver industry standard parasitic extraction tools / flows and capabilities for Intel's customers. Primary responsibility includes but not limited to enablement of PDK Custom and ASIC extraction flows/ methodologies and test the PDK collaterals. Job function includes assuring the quality of Extraction decks by setting up various flows/methodologies. Develops automation of QA flow methodologies for specific technology nodes to scale up QA coverage. Documents and monitors QA results. Deep understanding of technology changes at silicon level, able to interpret the front-end and back-end updates to execute multiple QA checks and methodologies. May also deliver design flows, guidelines, and tutorials through sample design databases, test chips, and libraries. Should be self-driven and able to take up new tasks. Leads root cause analysis for issues and continuously drives initiatives to enhance QA flows/ methodologies. Builds test structures and runs parasitic extraction (custom and asic) flows/methodologies. Should closely interact with EDA vendors for enablement of new features / additions to the existing flows / methodologies. Provide support for internal customers, collaborate with EDA vendors for enhancement of the flows based on customer requests. Should be proficient in documenting the observations made from the flows executed. Automation of the key capabilities for design productivity is add-on responsibility. Interfacing with PDK teams, EDA vendors, contracting employees from design service partners is a day-to-day job function.

Qualifications

Minimum Qualification: PhD in Electrical Engineering, Electronics Communication, Microelectronics or related fields with an emphasis in semiconductor device physics or VLSI. You must absolutely possess the minimum qualifications to be initially considered for this position. Experience would be obtained through your educational level research and/or relevant job internship experiences. Experience in custom layout design methodology, ASIC physical design / PnR flow and industry standard tools for extraction (StarRC, QRC). Candidate should have good knowledge on semiconductor physics, process technology, EDA tools and associated challenges for advance technology. Candidate should be well versed with different parameters to optimize flow in terms of quality and resources. Must be proficient in automation using skill, tcl, python, perl and other scripting languages. Ability to be cognitively flexible and agile in a fast changing software environment. Good interpersonal written and verbal communication skills and ability to work well in a team environment. Should be quick learner and ungate the execution with thorough understanding of issues and quickly converge to solutions.

Job Type

College Grad

Shift

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Legal Disclaimer

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